module aru_unary_neg (
    input logic               clk,
    input logic               rst_n,
          aru_unary_cfg_if.in u_aru_cfg_if,
          aru_payload_if.in   u_aru_pld_left_if,
          aru_payload_if.out  u_aru_pld_right_if
);

    logic lst_req_in_instr;
    assign lst_req_in_instr = u_aru_pld_right_if.sdb.eom && u_aru_pld_right_if.sdb.eon;

    // cfg handshake
    logic cfg_rdy, cfg_vld;
    assign cfg_vld = ~cfg_rdy;
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            cfg_rdy <= 1'b1;
        end else if (cfg_rdy == 1'b0) begin
            if (u_aru_pld_right_if.vld && u_aru_pld_right_if.rdy && lst_req_in_instr) begin
                cfg_rdy <= 1'b1;
            end
        end else begin
            if (u_aru_cfg_if.vld && u_aru_cfg_if.rdy) begin
                cfg_rdy <= 1'b0;
            end
        end
    end

    aru_dat_t neg_out;
    genvar i;
    for (i = 0; i < `P_ARU * `N0; i = i + 1) begin : gen_neg
        always_ff @(posedge clk or negedge rst_n) begin
            if (!rst_n) begin
                neg_out.dat[i].sign <= 1'b0;
                neg_out.dat[i].exp  <= 8'b0;
                neg_out.dat[i].mant <= 7'b0;
            end else begin
                // BF16 取负：只翻转符号位
                neg_out.dat[i].sign <= ~u_aru_pld_left_if.dat.dat[i].sign;
                neg_out.dat[i].exp  <= u_aru_pld_left_if.dat.dat[i].exp;
                neg_out.dat[i].mant <= u_aru_pld_left_if.dat.dat[i].mant;
            end
        end
    end


    aru_dat_t delayed_dat;
    common_delay_line #(
        .WIDTH(`P_ARU * `N0 * $bits(bf16_t)),
        .DEPTH(1)
    ) u_data_delay_line (
        .clk  (clk),
        .rst_n(rst_n),
        .en   (u_aru_pld_right_if.rdy && cfg_vld),
        .data_in  (u_aru_pld_left_if.dat),
        .data_out (delayed_dat)
    );

    logic delayed_vld;
    common_delay_line #(
        .WIDTH(1),
        .DEPTH(1)
    ) u_valid_delay_line (
        .clk  (clk),
        .rst_n(rst_n),
        .en   (u_aru_pld_right_if.rdy && cfg_vld),
        .data_in  (u_aru_pld_left_if.vld),
        .data_out (delayed_vld)
    );

    aru_sdb_t delayed_sdb;
    common_delay_line #(
        .WIDTH($bits(aru_sdb_t)),
        .DEPTH(1)
    ) u_sdb_delay_line (
        .clk  (clk),
        .rst_n(rst_n),
        .en   (u_aru_pld_right_if.rdy && cfg_vld),
        .data_in  (u_aru_pld_left_if.sdb),
        .data_out (delayed_sdb)
    );

    // Interface assignments - use correct port names
    assign u_aru_pld_left_if.rdy  = u_aru_pld_right_if.rdy && cfg_vld;
    assign u_aru_pld_right_if.vld = delayed_vld && cfg_vld;
    assign u_aru_pld_right_if.dat = u_aru_cfg_if.en ? neg_out : delayed_dat;
    assign u_aru_pld_right_if.sdb = delayed_sdb;



endmodule
